LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(A,B,C,D,E:IN BIT;
S0,S1,S2:IN BIT;
Y:OUT BIT);
END ENTITY mux21;
ARCHITECTURE connect OF mux21 IS BEGIN
Y<=A WHEN S0='0',S1='0',S2='1'
Y<=B WHEN S0='0',S1='1',S2='0’
Y<=C WHEN S0='0',S1='1',S2='1'
Y<=D WHEN S0='1',S1='0',S2='0' ELSE
E;
END ARCHITECURE commect;



哪位达人来修改一下！


[ 此帖被25091010在2008-04-13 21:25重新编辑 ]

我把你的程序改了，你的基本意思没怎么改;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY mux21 IS
PORT(A,B,C,D,E:IN BIT;
Sel:IN std_logic_vector(2 downto 0);
Y:OUT BIT);
END ENTITY mux21;
ARCHITECTURE connect OF mux21 IS
BEGIN
process(sel)
begin
if(sel="001")then
Y<=A;
elsif(sel="010")then
Y<=B;
elsif(sel="011")then
Y<=C;
elsif(sel="100")then
Y<=D;
else
Y<=E;
end if;
end process;
END  connect;