LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(A,B,C,D,E:IN BIT;
S0,S1,S2:IN BIT;
Y:OUT BIT);
END ENTITY mux21;
ARCHITECTURE connect OF mux21 IS BEGIN
Y<=A WHEN S0='0',S1='0',S2='1'
Y<=B WHEN S0='0',S1='1',S2='0’
Y<=C WHEN S0='0',S1='1',S2='1'
Y<=D WHEN S0='1',S1='0',S2='0' ELSE
E;
END ARCHITECURE commect;



哪位达人来修改一下！


[ 此帖被25091010在2008-04-13 21:25重新编辑 ]