module controller(send_floor,stop,up,clk);
input up;
input stop;
input clk;
reg upin;
reg stopin;
reg current_up,next_up;
reg send_floor;
output send_floor;

parameter
busy=1'b1,
idle=1'b0,
send=1'b1,
nsend=1'b0;

initial
begin
current_up=0;
end

always @(posedge clk)
begin
upin<=up;
stopin<=stop;
end


always @(posedge clk)
begin
case(current_up)
idle:begin
if(upin)
begin
next_up<=busy;
send_floor<=send;
end
else
next_up<=idle;
end
busy:begin
if(stopin)
begin
next_up<=idle;
send_floor<=nsend;
end
else
next_up<=busy;
end
default:next_up<=current_up;
endcase
current_up<=next_up;

end

endmodule

我也不是很懂,不过我把output的声明提到reg的前面我就编译通过了

module controller(send_floor,stop,up,clk);
input up;
input stop;
input clk;
output send_floor;
reg upin;
reg stopin;
reg current_up,next_up;
reg send_floor;


楼主第一次编就编这么难的程序啊?