UPDATED Researchers with the University of California at Santa Barbara, working in conjunction with Intel, announced Monday the next step in their joint plans to produce an entirely solid-state photonic processor assembly - a chip which processes data as light waves, without the need for microscopic, yet movable, parts.
The last major hurdle to being able to produce a fully fabricated, solid-state optical processor using on-board lasers involved the bonding process, it turned out.
Intel’s goal, stated today, is to be able to mass-produce a terabit-per-second optical networking processor chip. Though the company was at first unwilling to set a timeline, Dr. Mario Paniccia, director of Intel’s Photonics Technology Lab, today accepted a five- to ten-year timeframe, when finally pinned down by Insight64 analyst Nathan Brookwood during a conference call today that originated from a photonics conference in Hawaii.
Intel announced last November, along with the UCSB team, that it had developed a recipe for a ceramic material based on indium phosphide, that could produce a monochromatic wavelength of laser light when electricity is applied to it, and could also be produced as a wafer that bonds to a silicon substrate. That major development eliminated the need for movable gratings that, in silicon wafers produced since 2002, refract laser light from a multiple-wavelength source, so that a single wavelength could emerge.
A single-wavelength light source is critical, because modulations to that beam of infra-red light will be interpreted as data, so it needs to be a simple and regular as possible.
As Intel’s and the University of California at Santa Barbara’s lead engineers explained in a conference call from Hawaii earlier this afternoon, indium phosphide was chosen because it emits light predictably at regular wavelengths when voltage is applied to it. It’s obviously not silicon nor a silicate, so if silicon – obviously, Intel’s specialty – is to be used to guide light produced by an indium phosphide laser, there needs to be some way to offload the light from the laser onto the waveguide. In previous prototypes, this was done using moving parts, which can’t be expected to work in a production environment.
With a novel bonding process called evanescent coupling that takes place between the indium phosphide layer and the silicon waveguide layer, the surfaces of both layers are coated with an oxygen plasma. This causes both surfaces to oxidize, forming what Intel is calling a “glass glue.” When both oxidized surfaces are joined together under 300-degrees Celsius heat (which is half as hot as for other bonding processes), they create a transparent seal about 25 atoms thick, through which light from the laser is handed off to the silicon waveguide. This solves the need for active coupling devices, which would in effect use microscopic mirrors to pull off the same feat.
“We call it a quest to silconize photonics,” said Dr. Paniccia, “and there’s essentially six building blocks that you need to drive [it]: One, you need a light source to enable light into the chip. You need a way to guide the light – route it, split it, couple it, get it in and out of the chip efficiently. You need a way to modulate the data, to encode optical bits. You need a way to photodetect the light, and eventually convert the photons back to electrons. And even if you can build these devices, you still need a way to enable low-cost, high-volume assembly technology. Lastly, you need intelligence—you need the electronics to drive the circuits, to drive the photonics, and to do the computation."
“If you look at what’s happened over the last couple of years with silicon photonics around the world,” Dr. Paniccia continued, “it’s gone from a ‘PowerPoint technology’ [in presentations only] to a technology that’s quite viable. Two years ago, the fastest modulation in silicon was about 20 – 30 MHz. We went public in ’04 with 1 GHz modulation in silicon, a year later we demonstrated 10 Gbps, and since then, others have demonstrated around the world. These are three orders of magnitude improvement in performance in less than two years, and people are now talking about 40 and 100 Gbps, potentially, in silicon. These are fundamental changes, leaps in performance.”
Intel is looking here for the ultimate triple-play: a processor that will be introduced in fiberoptic networking, though could conceivably be integrated into general computing platforms in subsequent years, that is faster, smaller, and less expensive to produce, all at the same time.
Indium phosphide was chosen for the laser layer, Dr. John Bowers of UCSB told BetaNews today, because its physical structure enables what is called a direct band gap. It’s essentially a very simple semiconductor, where the combination of electrons and holes (absence of electrons) is recreated in a single step, rather than several, after the incoming current into the semiconductor is enticed to cross the junction.
Silicon and germanium, by contrast, enable an indirect band gap - though it’s still possible to reassemble the original electron/hole stream, it takes a few more steps, and is thus more physically complex. The combination for an indirect band gap is called a phonon process, as opposed to a photon process, where phonons are, simply put, heat.
As Dr. Paniccia said today, this heat dissipation may not be a problem. The fact that these processor enable higher-speed communications in the first place, could enable new server cooling architectures where, for instance, banks of memory are stationed meters away from the CPU instead of inches, thus reducing heat interaction.
“Today, basically the entire silicon photonics industry is based on indium phosphide devices,” Dr. Bowers continued, “and the data [communications] industry is based on gallium arsenide devices. But they’re [both] III-V materials because they’re high-gain.”
Conceivably, Dr. Bowers implied, this could become a political issue, as entire industries don’t give up their existing processes on a whim (the history of superconductivity being a prime example). However, Intel’s presence at today’s datacom conference – perhaps a novelty in itself, for this particular group – may be to help lead what he calls the “sea change.”
In previous silicon laser prototypes, the cost recoveries from the elimination of copper have been offset by the use of movable elements – gratings and mirrors, essentially – for guiding the modulated light beam throughout the processor. With today’s announcement that getting light onto the waveguide can take place literally through the glue holding them together, it now appears not only will optical processors become less expensive to produce over time, but will no longer require the use of a software-based monitoring system to ensure data integrity.
Dr. Paniccia said current hybrid silicon laser prototypes use 400 nm lithography, whereas production versions could eventually produce hundreds, or more than a thousand, silicon lasers simultaneously on a single wafer, for a cost of pennies per unit. At that time, he said, Intel will be able to take advantage of 65 nm production. But by the time that five- to ten-year timeframe plays out, he was asked, won’t 45 nm lithography already be in full swing?
With even 65 nm technology, he responded, “we will draft Moore’s Law,” borrowing phrases from both Intel’s history and NASCAR racing. “So we don’t have to be at the leading edge; we can be a generation or two behind, just like we are with chipsets...which allows us to take advantage of depreciated factories. We will always gain by better lithography, so as we move forward, we will take advantage of the lithography that’s available or that’s cost-effective; in terms of improving the laser performance, you will always benefit from better lithography, smaller devices, smoother surfaces."
“That’s really the nice thing [about] silicon photonics in general,” Dr. Paniccia continued. “As you go forward, you continue to improve and draft the investment that the industry is making, without having to be at the leading edge right from the beginning.”
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