第一个

SoC ASIC Verification Engineer  Vacancy:1
Job Description :
Ø Develop and maintain ASIC/SoC testbench environment at block and/or system level using Verilog, Systemc, PLI/C or SystemVerilog.
Ø Develop and execute various tests to verify the chip functionality according to Chip Spec.
Ø Create verification plans and define application tests to meet the requirement of functional/code coverage.
Ø Develop and maintain script/Makefile for simulation compile/running, regression running, parameterized simulation, result analysis, etc.
Job Requirements :
Ø BSEE, MSEE with 4+ years experience preferred；
Ø Must be capable of independently developing test plans, test benches, tests；
Ø Strong design background and must be capable of debugging RTL, gate sim debug capability is a plus.
Ø Hand-on verification experience on SoC, the areas include ARM, AMBA, DDR2, PCIe, USB, CODEC, etc.
Ø Good knowlege of the whole ASIC/SoC development flow.
Ø Experience with at least one scripting language, TCL or Perl is preferred.
Ø Good English written and communication skills.
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第二个

Senior SoC ASIC Verification Engineer  Vacancy:1
Job Description :
Ø Instrumental in the development of infrastructure for the validation of ARM AMBA-based architectures and the verification of SoC hardware.
Ø Additional duties include the development of directed and random hardware verification environments, and the application of those environments to SOC verification
Ø Integration of VIP UVC and functional verification agents in OVM verification environment to support coverage-driven verification
Job Requirements :
Ø Extensive Verilog experience with SOC verification environments.
Ø Verification experience on ARM, AXI, and DMA with VIP UVC
Ø Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
Ø Experience with high level verification languages such as SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
Ø Shell scripts and Perl expertise, create runsim, lsf, regression management scripts
Ø Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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第三个

Senior SoC ASIC Design/Verification Engineer  Vacancy:1
Job Description :
Ø Integration of ARM processor and AMBA bus for SoC;
Ø Integration of H264 Codec , DDR, USB and PCIe for SoC;
Ø Design SoC-level logic including clock, reset, and DFT;
Ø Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
Ø Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.
Job Requirements :
Ø 5+ years experience on SoC design and integration;
Ø Hand-on experience in ASIC flow;
Ø Experience of ARM/AMBA integration and/or verification;
Ø Experience of DMA design and/or verification;
Ø Experience of H264 Codec & DDR SoC integration and verification
Ø Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
Ø Specman ERM and OVM verification experience is a big plus

不是英格索兰，哥不去

1楼不是我~~~~
是谁在用我的号发帖？？？？？

编辑了
做人要厚道


[ 此帖被白菜道士在2010-01-22 18:38重新编辑 ]

Quote:

引用第10楼nooo于2010-01-22 18:46发表的  :

你在里面能出的来么

这个星期放风提前了

Quote:

引用第18楼枫姐姐于2010-01-22 20:45发表的  :

看样子应该是个牛X公司

能有英格索兰1/100000000牛X吗？？？

Quote:

引用第20楼raulqql于2010-01-22 20:58发表的  :


烦不烦啊你。
受不了你了。

来打我嘛~~~~
鄙视的飘走~~

Quote:

引用第24楼jerryliu于2010-01-23 00:10发表的  :

在楚雄呆过一周，哈哈~~~

那一周尽吃野猪肉来着了...
就去旁边的彝人古镇玩了玩。。。

彝人古镇好所在啊~~~
[屏蔽]来楚雄的时候都特意去了的~~~

可惜我是在大平坝，不晓得什么时候才能去彝人古镇了

Quote:

引用第26楼枫姐姐于2010-01-23 13:45发表的  :

[屏蔽]去了趟展讯，带去了国家的支持和慰问，于是展讯在全年亏损的状况下照样涨薪，还发了4个月工资的年终奖

他什么时候来哈我们大平坝嘛。。。。。。
给我也涨点薪