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灌水乐园 大杂烩
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最近有没有在找工作的。。让我赚点推荐费吧
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最近有没有在找工作的。。让我赚点推荐费吧
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filif
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5come5帮你背单词 [
dynamic
/dai'n
æ
mik/
a. 有生气的,能活动的,有力的,动力的,动态的
]
最近有没有在找工作的。。让我赚点推荐费吧
第一个
SoC ASIC Verification Engineer Vacancy:1
Job Description :
Ø Develop and maintain ASIC/SoC testbench environment at block and/or system level using Verilog, Systemc, PLI/C or SystemVerilog.
Ø Develop and execute various tests to verify the chip functionality according to Chip Spec.
Ø Create verification plans and define application tests to meet the requirement of functional/code coverage.
Ø Develop and maintain script/Makefile for simulation compile/running, regression running, parameterized simulation, result analysis, etc.
Job Requirements :
Ø BSEE, MSEE with 4+ years experience preferred;
Ø Must be capable of independently developing test plans, test benches, tests;
Ø Strong design background and must be capable of debugging RTL, gate sim debug capability is a plus.
Ø Hand-on verification experience on SoC, the areas include ARM, AMBA, DDR2, PCIe, USB, CODEC, etc.
Ø Good knowlege of the whole ASIC/SoC development flow.
Ø Experience with at least one scripting language, TCL or Perl is preferred.
Ø Good English written and communication skills.
————————————————————————————————————————————
第二个
Senior SoC ASIC Verification Engineer Vacancy:1
Job Description :
Ø Instrumental in the development of infrastructure for the validation of ARM AMBA-based architectures and the verification of SoC hardware.
Ø Additional duties include the development of directed and random hardware verification environments, and the application of those environments to SOC verification
Ø Integration of VIP UVC and functional verification agents in OVM verification environment to support coverage-driven verification
Job Requirements :
Ø Extensive Verilog experience with SOC verification environments.
Ø Verification experience on ARM, AXI, and DMA with VIP UVC
Ø Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
Ø Experience with high level verification languages such as SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
Ø Shell scripts and Perl expertise, create runsim, lsf, regression management scripts
Ø Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
————————————————————————————————————————————
第三个
Senior SoC ASIC Design/Verification Engineer Vacancy:1
Job Description :
Ø Integration of ARM processor and AMBA bus for SoC;
Ø Integration of H264 Codec , DDR, USB and PCIe for SoC;
Ø Design SoC-level logic including clock, reset, and DFT;
Ø Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
Ø Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.
Job Requirements :
Ø 5+ years experience on SoC design and integration;
Ø Hand-on experience in ASIC flow;
Ø Experience of ARM/AMBA integration and/or verification;
Ø Experience of DMA design and/or verification;
Ø Experience of H264 Codec & DDR SoC integration and verification
Ø Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
Ø Specman ERM and OVM verification experience is a big plus
Posted: 2010-01-22 17:44 |
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月夜狼歌
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积极开展批筛与自我批筛
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7349
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4
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766
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最后登陆: 2012-10-25
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5come5帮你背单词 [
forbid
/f
ə
'bid/
vt. 禁止,阻止
]
小F一出来就是猛贴
Posted: 2010-01-23 14:13 |
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