招-聘行程：城市 宣讲会大学 地址 日期 时间 教室
成都 成都电子科技大学 成都市建设北路二段四号 2011-10-12 18:30 一教104会议厅
上海 上海交通大学 闵行区东川路800号 2011-10-19 18:30 微电子大楼一楼报告厅
复旦大学 浦东新区张江张衡路825号 2011-10-20 18:30 行政楼106报告厅
杭州 浙江大学 杭州市西湖区浙大路38号 2011-10-25 19:00 永谦活动中心排练厅
南京 东南大学 南京市玄武区东南大学四牌楼2号 2011-10-27 18:30 群贤楼三楼报告厅
招-聘职位：1，
SPD-Read Channel-Verification Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
A qualified applicant for this position would be responsible to do storage read channel functional verification. Duties will include functional verification of Storage read channel mixed-signal IP. Candidate will be expected to contribute to design and development of System Verilog based verification environment and will be responsible for verification closure of block/chip/system level functions for mixed signal based IP. Knowledge of design/architecture is necessary. Experience with Verilog, System Verilog and functional coverage methodologies are required. Must be willing to follow a disciplined verification methodology and to work closely with a multi-location, international design team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
Good understanding of Digital Signal Processing. Knowledge of VLSI design flows. Expertise in System Verilog. Familiarity of high level programming language.
Knowledge of verification methodologies including functional coverage and constrained random testing.
Good understanding of Digital and Analog Circuits.
Very good analytical/debugging skill.
Good verbal and written communication skills, to work with globally distributed team.
Education/Certifications:
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
2，
SPD-Read Channel-Analog (AMS) Behavioral ModelerDESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
A qualified applicant for this position would be responsible to work within a Product Development Team to create behavioral models for Read Channel analog design blocks and do functional verification. Close interaction with the analog and digital design teams is required. Full chip verification of read channel designs which incorporate the analog models is required. Ability to use both digital and analog simulators is required. Must be willing to follow a disciplined design approach and to work closely with a multi-location, international team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
Analog/Mixed-signal design Major.
Expertise of digital design.
Experience with analog and digital Cadence-based simulation tools and system Verilog/AMS modeling language.
Strong written and verbal communication skills.
Read channel application experience (desired).
Education/Certifications:
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
3.
SPD-Preamp-Analog/Mixed Signal Design Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
LSI's Storage Peripherals Group is looking for an analog IC designer to join the pre-amplifier design team.
Design team members define, create and modify high-speed custom integrated circuits for hard disk drive (HDD) and tape recording products using leading edge CMOS and SiGe BiCMOS technologies. Team members support the entire product life cycle beginning with design and moving through test, qualification, release to production and ramp to volume. A qualified applicant for this position would design high speed analog and mixed-signal integrated circuits within custom chips for the hard disk drive and tape drive industry. Work directly with customer team to determine system requirements, write specifications and guide customers in the use of pre-amplifier products. Use high speed electronic characterization equipment to evaluate and debug the functionality of the design once the part is fabricated in silicon. Provide technical leadership through all phases of product development including test, yield, characterization, reliability analysis, qualification and release to manufacturing.
PREFERRED EXPERIENCE:
Experience with analog and mixed signal IC product design, integration and verification is required.
Strong physical layout knowledge and parasitic component understanding essential.
Process and device physics knowledge critical.
Proven skills using electronic measurement equipment in a lab environment.
Expertise in applied magnetism and recording a strong plus.
Education/Certifications:
Preferred Degree: MS or PhD
Preferred Major: Electrical Engineering or related discipline
4，
SPD-Read Channel-Validation Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
This position is part of the LSI’s world-lead magnetic recording system design validation team, and focus on mixed-signal and high speed read channel/SoC debugging, characterization and validation, proto device bring up. A qualified applicant for this position would develop and set up the automation bench test equipment system. Develop automated scripts to program the device and test equipment, and automate data collection and processing. Work with architecture and design team to verify the latest IP, define test plan, characterization on high speed (>4GHz) mixed-signal SoC and errata corrective actions. Organize bench data into technical reports for reference and presentation. Presentation of data to both internal and external customers.
PREFERRED EXPERIENCE:
Be expected to be highly motivated and resourceful in troubleshooting and problem solving.
A thorough knowledge of electronic circuits and systems with practical experience in analog and digital electronic circuit design and debug.
Good at usage of advanced waveform generators, oscilloscopes, network analyzers and logic analyzers.
Be expert in data analysis techniques and in various scripting languages (Perl, TCL, and Python). Experience in lab automation (such as through GPIB, VBS, LabView scripting) is also desirable.
Experiences in RF, high speed and storage system (HDD, Flash etc) measurement is a plus.
Knowledge on and/or experience in read channel/SoC, magnetic recording is a strong plus.
Knowledge on the error decoding like LDPC, MAP, SOVA is a strong plus.
Excellent written and good English communication skills are required.
Education/Certifications:
Preferred Degree: BS or MS
Preferred Major: Electrical Engineering or related discipline
5.
SPD-Preamp-Verification EngineerDESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
LSI's Storage Peripherals Division is seeking an experienced verification design engineer to join the pre-amplifier design team. Preamp design team members define, create, modify and verify high-speed custom integrated circuits for hard disk drive (HDD) and tape recording products using leading edge CMOS and BiCMOS technologies. A qualified applicant for this position would work with a Preamp Development team to create Verilog testbench components and simulation environment. Create product test plans, test cases and perform simulation and debug of Storage Preamp mixed-signal devices. Must be experienced with Verilog and Verilog AMS and knowledgeable with functional coverage methodologies. Has ability to follow a disciplined verification methodology and work closely with a multi-location, international design team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
Conversant with Verilog, SystemVerilog, Specman, Perl/Python/Tcl scripts, Makefile and C++
Knowledgeable with functional coverage methodologies and constrained random testing
Strong communication skills (must be proficient in both spoken and written English)
Proven analytical skills (application of math and physics to solve problems)
Experience with Assertion or Formal Verification a plus
Conversant with Verilog-AMS/Verilog-A and Analog Behavior Modeling would be a plus
Understanding of silicon process technologies (CMOS and Bipolar) and device physics would be a plus.
Education/Certifications:
Required Degree: BS
Preferred Degree: MS or PhD
Preferred Major: Electrical Engineering or related discipline
6，
SPD-Preamp-Validation Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
This position is part of the LSI’s world-leading head-to-host recording system design validation team, and focus on high speed pre-amplifier validation and debug. A qualified applicant for this position would set up bench test equipment and perform characterization measurements on high speed (>4GHz) mixed signal IC's, paying careful attention to measurement accuracy and repeatability and test condition coverage. Design and layout evaluation PCBs, paying careful attention to high speed signals and board component parasitic. Develop automated scripts and program test equipment to automate data collection and report generation. Where automated measurements are not practical, manual data collection is to be performed. Work with design and other characterization teams in design verification and characterization and errata corrective action, as well as work with program management, test and product engineering to insure timely delivery of fully verified silicon. Support bench application engineers with in-depth customer specific measurements and failure analysis. Organize bench data into technical reports for reference and presentation. Consolidate presentation of data to both internal and external customers. Manage local subcontractors that perform flip chip and board assembly. Work with program management, design, test and product engineering as part of a product support team to insure timely delivery of fully validated silicon.
PREFERRED EXPERIENCE:
Investigative and analytical mindset, with a strong interest in electronics and technical work.
A thorough knowledge of electronic circuits and systems with practical experience in analog and digital electronic circuit design and debug.
Experience or background with one of the following areas is preferred
Experiences in RF, high-speed connector (SATA, DDR etc), gesture recognition or storage system (HDD, Flash etc) measurement.
Experiences in Cadence Allegro HDL (Concept) PCB development. Allegro layout experience is a plus.
Developing the automation programming: VBS, Labview & TestStand. IVI driver coding experience is a strong plus.
Complete the FPGA design with 200MHz+ data paths before.
Expertise in applied magnetism and recording a strong plus.
Good communication skills, especially in technical writing and reporting.
Education/Certifications:
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
7.
NCD-Design and Verification Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
A qualified applicant for this position would work with a product development team on networking IC design, verification, and post-silicon validation. Design tasks will include reviewing and studying product/system requirements, develop hardware design specification, digital logic design using HDL, RTL review, simulation debug, close timing together with design implementation team. Verification tasks will include reviewing RTL architectural and implementation specifications, developing verification plan, developing reusable block and system level verification components/environments using high level verification language to verify the functionalities and performance of networking ICs, which are advanced multi-core networking processors, multi-service processors, multi-core media and baseband processors and target for wireline and wireless networking infrastructure. Validation tasks will include FPGA design, verification of chip’s functionalities, performance, and reliability on a system.
PREFERRED EXPERIENCE:
Digital logic design skills using hardware description languages.
Experience on high level verification languages and advanced verification methodology.
Computer networking and telecommunication knowledge.
Object oriented programming knowledge.
Scripting skills, such as Shell, Perl and TCL.
Good written and verbal communication skills.
Education/Certifications:
Preferred Degree: MS
Preferred Major: Electrical Engineering, Microelectronics or related discipline
8.
WMO-Product Engineer/Test Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
A qualified applicant for Product Engineer position would support new product release and manage product characterization for eventual robust production release. Drive yield improvement activities at both wafer sort and final test areas and work in conjunction with foundries to reduce product defectivity. Manage product costs and drive for cost reduction initiatives. Deploy yield engineering tools for analysis and drive for corrective actions. Analyze product return from customers to improve test coverage and reduce product dppm.
A qualified applicant for Test Engineer position would support prototype and production releases of new products. Manage debug of test program, design and debug of test hardware, and meet product release schedule. Support test program development for implementing changes in new test methodologies for test coverage improvement. Pursue Design for Test initiatives to optimize testability and achieve test cost reduction via test time reduction and multiple site test solutions for production release. Support test chip test development and characterization of new IP used in LSI products
PREFERRED EXPERIENCE:
Solid background of Digital and Analog circuit.
Good Communication Skills (Written & Oral) in English
Proficiency with 1+ computer programming language is a must, C/C++ and Pearl is plus
Good analytical skills and active learning
Statistics Analyzing knowledge is preferred.
ATE programming skills and semiconductor manufacturing industry knowledge would be essential.
Education/Certifications:
Required Degree: BS (Top scores in GPA)
Preferred Degree: MS (Top scores in GPA)
Preferred Major: Electrical Engineering or Microelectronics or Automation
9.
CSD-ASIC Customer Design Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
LSI Corporation offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing LSI's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 40nm/28nm designs.
Detail design tasks include
Presales support (die size support, memory generation, addressing customer questions and concerns.)
RTL analysis & synthesis
Top level and block level physical design Implementation (bonding, floor planning, power structure insertion, place and route, timing closure)
Test structure insertion/silicon testing debug
Formal verification
Static timing analysis
Cross talk analysis
Power verification
Physical verification
Overtime, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.
PREFERRED EXPERIENCE:
Candidates should have basic understanding about ASIC design flow and solid VLSI background.
Candidate s should have strong communications and problem solving skills.
Candidates with internship experience are a plus.
Candidates with experience in any one of following knowledge are a plus:
RTL Analysis/Synthesis/STA: An ideal candidate having some background or skills for the front-end of design implementation which includes RTL Analysis, Synthesis Strategies, and STA setup for complex ASIC environments and strategies for power management.
OR
Physical Design Implementation: An ideal candidate having some background in either the Physical. Design which includes floor planning, design closure, STA, and DRC & LVS skills.
OR
DFT: An ideal candidate having some background in DFT (Design for Test) which would include scan/TDF, TestKompress, Memory Bist and Bisr, and JTAG.
Education/Certifications:
Preferred Degree: MS
Preferred Major: Microelectronics or related discipline
10.
CSD-Package Design Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
As a member of package design group, support design of flip chip substrates, work closely with the LSI customers from design start to tooling completion steps. Work directly with program management, reliability, product engineering groups to align package design and materials necessary to support program schedule, and readiness for customer prototypes and production. Responsible for documentations associated with the substrate design release for tooling with the substrate suppliers as part of the design closure.
PREFERRED EXPERIENCE:
0-1 year experience in the design and implementation of multilayer BGA substrate technology for support of single or multi-chip package constructions.
Good hands on knowledge of Cadence APD design tool are required.
Good communication and written skills required for design engagement with internal engineering teams and external customers.
Must be detail oriented in design specifications, implementation, reviews with customers.
Background in organic or ceramic substrate manufacturing processes is desired.
Familiarity with the influence of physical design parameters affecting electrical/ thermal performance of packaging technologies desired.
Knowledge of flip chip assembly processes.
Familiar with electrical and thermal characteristics of packages.
Familiarity and hands on knowledge of Microsoft project, word, excel.
Education/Certifications:
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
11.
CSD-Signal Integrity Engineer (Modeling for Package Design) DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
As a member of package characterization group, support package electrical model extraction for flip-chip, wire-bond, and multi-component High Speed Advanced Integrated Circuit devices using a variety of Quasi-static and Full Wave commercial field solvers including Ansoft HFSS. Test and verify the resulting RLCG (Quasi-static) or S-parameter (Full Wave) models using hspice. Work closely with a global team of package layout engineers as well as a global Parallel Interface, High Speed Serial I/O (SerDes), and Power Domain Network Signal/Power integrity teams.
PREFERRED EXPERIENCE:
0-1 year experience extracting electrical models using commercial field solvers such as Ansoft HFSS.
Good communication and written skills required for design engagement with internal engineering teams and external customers.
Knowledge of IC Package design is beneficial (e.g. experience with Cadence APD).
Familiarity and hands on knowledge with Microsoft Word and Excel as well as simulation tools such as hspice.
Fluency in written and oral English is required.
Familiarity with electromagnetic field theory and microwave technique is a plus.
Education/Certifications:
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
公司为了招募优秀人才，欢迎大家去51job上投递简历，现在就可以开始了，当然，也可以发简历到我的邮箱，
lsiresumeuestc@163.com, 我会负责把简历直接转发给我们HR，校园招-聘的时候你的简历就会提前到达我们部门面试经理手里拉，当然你也可以选择校园招-聘的时候再投递简历。忘了介绍自己了？成电06年毕业的小兵一名，在公司2年拉！其实大家看看我ID的注册日期就知道了！哈哈
对了，中英文简历哦，邮件的标题写上自己想应聘的职位。
希望大家都找到满意的工作，过个好年啊，哈哈！
[ 此帖被成电的沉淀在2011-09-21 17:03重新编辑 ]
