自己照这Xilinx ISE 6.2b的Tutorials做的，但到了调用Modelsim进行"Generate Expected Simulation Results"时，报错：Error: can't read "FileWatch(fileName)": no such element in array
请问该如何解决？
报错全文如下：Launching Application for process "Generate Expected Simulation Results".
Reading D:/Modeltech_6.2b/tcl/vsim/pref.tcl
# 6.2b
# do Counter_TBW.ado
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity counter
# -- Compiling architecture behavioral of counter
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity counter_tbw
# -- Compiling architecture testbench_arch of counter_tbw
# -- Compiling configuration counter_cfg
# -- Loading entity counter_tbw
# -- Loading architecture testbench_arch of counter_tbw
# -- Loading entity counter
# vsim -lib work -t 1ps Counter_TBW
# // ModelSim SE 6.2b Jul 31 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Break in Process line__89 at f:/eda/xilinx/test/Counter_TBW.ant line 112
# Stopped at f:/eda/xilinx/test/Counter_TBW.ant line 112
Error: can't read "FileWatch(fileName)": no such element in array
Counter.vhdl内容如下：library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(3 downto 0);
COUNT: inout STD_LOGIC_VECTOR(3 downto 0)
);
end Counter;
architecture Behavioral of Counter is
begin
process (CLK, RESET)
begin
if RESET='1' then
COUNT <= "0000";
elsif CLK='1' and CLK'event then
if CE='1' then
if LOAD='1' then
COUNT <= DIN;
else
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
Counter_TBW.ant内容如下：-- F:\EDA\XILINX\TEST
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu May 01 10:22:25 2008
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY Counter_TBW IS
END Counter_TBW;
ARCHITECTURE testbench_arch OF Counter_TBW IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\eda\xilinx\test\Counter_TBW.ano";
COMPONENT counter
PORT (
CLK : In std_logic;
RESET : In std_logic;
CE : In std_logic;
LOAD : In std_logic;
DIR : In std_logic;
DIN : In std_logic_vector (3 DOWNTO 0);
COUNT : InOut std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
SIGNAL CLK : std_logic;
SIGNAL RESET : std_logic;
SIGNAL CE : std_logic;
SIGNAL LOAD : std_logic;
SIGNAL DIR : std_logic;
SIGNAL DIN : std_logic_vector (3 DOWNTO 0);
SIGNAL COUNT : std_logic_vector (3 DOWNTO 0);
BEGIN
UUT : counter
PORT MAP (
CLK => CLK,
RESET => RESET,
CE => CE,
LOAD => LOAD,
DIR => DIR,
DIN => DIN,
COUNT => COUNT
);
PROCESS -- clock process for CLK,
VARIABLE TX_TIME : INTEGER :=0;
PROCEDURE ANNOTATE_COUNT(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC,string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'(",COUNT,"));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, COUNT);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 10 ns;
TX_TIME := TX_TIME + 10;
CLK <= transport '1';
WAIT FOR 10 ns;
TX_TIME := TX_TIME + 10;
ANNOTATE_COUNT(TX_TIME);
WAIT FOR 40 ns;
TX_TIME := TX_TIME + 40;
CLK <= transport '0';
WAIT FOR 40 ns;
TX_TIME := TX_TIME + 40;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for CLK
VARIABLE TX_OUT : LINE;
BEGIN
-- --------------------
RESET <= transport '1';
CE <= transport '0';
LOAD <= transport '0';
DIR <= transport '0';
DIN <= transport std_logic_vector'("0000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
RESET <= transport '0';
DIR <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
CE <= transport '1';
-- --------------------
WAIT FOR 1460 ns; -- Time=1660 ns
-- --------------------
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
CONFIGURATION counter_cfg OF Counter_TBW IS
FOR testbench_arch
END FOR;
END counter_cfg;
