Quote:
引用第106楼calitrean于2009-04-14 12:54发表的 :
难道是把INTEL芯片上的LOGO打磨了换个你的LOGO，两天就搞定了 
那个仪器很贵
老板喊精简成本
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module control (opcode,IorD,mem_en,rd_wr,fetch,Rd_sel,imm_src,ra_wr,reg_wr,reg_src,
B_sel,A_sel,cmpr,func,alu_out,jz,jnz,pc_update,rst,clk);
input [3:0] opcode;
output IorD,mem_en,rd_wr,fetch,Rd_sel,ra_wr,reg_wr,reg_src;
output cmpr,alu_out,jz,jnz,pc_update;
output [1:0] func,A_sel,imm_src,B_sel;
input rst,clk;
reg [20:0] temp;
reg [1:0] current_state;
assign IorD=temp[20];
assign mem_en=temp[19];
assign rd_wr=temp[18];
assign fetch=temp[17];
assign Rd_sel=temp[16];
assign imm_src=temp[15:14];
assign ra_wr=temp[13];
assign reg_wr=temp[12];
assign reg_src=temp[11];
assign B_sel=temp[10:9];
assign A_sel=temp[8:7];
assign cmpr=temp[6];
assign func=temp[5:4];
assign alu_out=temp[3];
assign pc_update=temp[2];
assign jz=temp[1];
assign jnz=temp[0];
//opcdes(3): 0=add, 1=sub, 2=and, 3=or,
//opcdes(2): 4=slt, 5=seq,
//opcdes(3): 6=lw
//opcdes(3): 7=sw
//opcdes(3): 8=addi, 9=mov
//opcode(2): 10~14=j type
/* state transition*/
always @ (posedge clk) begin
if (!rst) current_state<=0;
else begin
case (current_state)
1: current_state<=0;
2: current_state<=3;
3: current_state<=0;
0: begin
case (opcode)
4,5,10,11,12,13,14: current_state<=1;
0,1,2,3,6,7,8,9: current_state<=2;
default: current_state<=0;
endcase
end
default: current_state<=0;
endcase
end
end
//opcdes(3): 0=add, 1=sub, 2=and, 3=or,
//opcdes(2): 4=slt, 5=seq,
//opcdes(3): 6=lw
//opcdes(3): 7=sw
//opcdes(3): 8=addi, 9=mov
//opcode(2): 10~14=j type
/*control signal generation*/
always @ (current_state) begin
case (current_state)
0: temp=21'b0111_0000_0001_01000_0100;
1: begin //execution of 2 step instr
case (opcode)
4: temp=41; //slt
5: temp=51; //seq
10: temp=101; //j
11: temp=111; //jz
12: temp=121; //jnz
13: temp=131; //jal
14: temp=141; //jr
default:temp=0; //lock all registers and ram
endcase
end
2: begin //execution of 3 step instr
case (opcode)
0: temp=1; //add
1: temp=11; //sub
2: temp=21; //and
3: temp=31; //or
6: temp=61; //lw
7: temp=71; //sw
8: temp=81; //addi
9: temp=91; //mov
default:temp=0; //lock all registers and ram when error
endcase
end
3: begin //result store of 3 step instr
case (opcode)
0: temp=2; //add
1: temp=12; //sub
2: temp=22; //and
3: temp=32; //or
6: temp=62; //lw
7: temp=72; //sw
8: temp=82; //addi
9: temp=92; //mov
default:temp=0; //lock all registers and ram when error
endcase
end
default: temp=0;
endcase
end
// case
// case (current_state[1:0])
// 2'b00:temp=21'b0111_0000_0001_01000_0100; //fetch&decode
// 2'b01: //
// 2'b10;
// default:temp=21'b0;
// endcase
endmodule
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