仿真如下程序

`timescale 1ns/1ns
`include "compare.v"

module ceshi;
reg a,b;
wire equal;
initial
begin
  a=0;
  b=0;
  #100 a=0;b=1;
  #100 a=1;b=1;
  #100 a=1;b=0;
  #100 a=0;b=0;
  #100 $stop;
  end

compare m(.equal(equal),.a(a),.b(b));
endmodule

老是出现"Error: Can't synthesize current design -- design does not contain any logic"
傻子原因啊??

这种延时不能用在QUARTUS中，把#100 改为计数器延时

`timescale 1ns/1ns
#100 a=0;b=1;
  #100 a=1;b=1;
  #100 a=1;b=0;
  #100 a=0;b=0;
  #100 $stop;
以上是非可综合语法。。。。。

不会Vevilog
之用ＶＨＤＬ