//VHDL原程序，应该没有错误的
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ha is
port(clk:in std_logic;
dclk:out std_logic);
end ha;
architecture Behavioral of ha is
signal count: integer range 0 to 10;
signal clk10: std_logic;
begin
process(clk)
begin
if count=10 then
clk10<=not clk10;
count<=1;
else count<=count+1;
end if;
end process;
dclk<=clk10;
end Behavioral;
//测试文件，也因该是没问题的撒
-- VHDL Test Bench Created from source file ha.vhd -- 22:01:45 04/12/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ha_test_vhd_tb IS
END ha_test_vhd_tb;
ARCHITECTURE behavior OF ha_test_vhd_tb IS
COMPONENT ha
PORT(
clk : IN std_logic;
dclk : OUT std_logic
);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL dclk : std_logic;
BEGIN
uut: ha PORT MAP(
clk => clk,
dclk => dclk
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
clk<='1';wait for 15.625 ns;
clk<='0';wait for 15.625 ns; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
好像两个文件都没问题，可是出来的图形错误，DCLK是一个无关态，不知道那里错拉，是不是软件的BUG，
今天在实验室得到了正确的波形图，可是在自己的机子上却出不了
请教高手，谢谢诶
